The applicant of the present invention proposes various analog architectures in un LSI, with a view to realizing highly accurate analog data processing. This requires that both capacitance and other elements are accurate. Such accuracy in capacitance capacity is proposed with respect to the capacitance-forming method in Japanese Patent Laid-Open Publication No. 7-211860.
In Japanese Patent Laid-Open Publication No. 7-211860, adjacent unit capacitances in a two-dimensional unit capacitance are divided into independent capacitances.
FIG. 5 shows a capacitance with such a structure, in which a plurality of unit capacitances 1 are two-dimensionally arrayed and connected to a plurality of conductors 2. A common electrode faced to each unit capacitor electrode (not shown) is formed in a layer adjacent to these unit capacitor electrodes and connected to a plurality of conductors 3 formed in the same layer where conductors 2 are formed. To each unit capacitor electrode, a metal terminal-contacting portion penetrating from the layer containing a unit capacitor electrode to the layer containing conductors 2 are connected. In the layer containing conductors 2, an approximately rectangular metal terminal head 5 is connected to metal terminal-contacting portion 4. Metal terminal head 5 is shown in FIG. 6. To the common electrode, metal terminal-contacting portion 6 from the electrode layer opposite to the layer of conductors 2 is connected. In the layer of conductors 3, approximately rectangular metal terminal-contacting portion 7 is formed in metal terminal-contacting portion 6. The adjacent unit capacitor electrodes in unit capacitor electrode rows are connected to a different conductor 2 to suppress the dispersion of capacitive accuracy.